A complete reference of all Intel 8086 instructions, organised by category, with clock counts sourced from the Intel 8086 Family User’s Manual (1979). Each category links to the series post where that group is explained in depth with examples and flag effects. For memory operands, add EA clock costs: [BX]/[SI]/[DI]=5, [BP]=5, [BX/BP+disp]=9, [BX+SI]/[BP+DI]=7, [BX+DI]/[BP+SI]=8, [BX+SI/BP+DI+disp]=11, [BX+DI/BP+SI+disp]=12. Segment override adds 2.
1. Data Transfer Instructions
In-depth coverage: Register Reference · Stack Operations
| Instruction | Clocks | Explanation | Example |
|---|---|---|---|
MOV | 2–9+EA | Copy data from source to destination | MOV AX, BX — copies BX into AX (2 clocks) |
PUSH | 15 | Decrement SP by 2, write register to SS:SP | PUSH AX |
POP | 12 | Read word from SS:SP into register, increment SP by 2 | POP BX |
PUSHF | 14 | Push FLAGS register onto stack | PUSHF |
POPF | 12 | Pop word from stack into FLAGS register | POPF |
XCHG | 3–4 | Exchange two operands atomically (3 if one is AX) | XCHG AX, BX |
IN | 10–14 | Read byte/word from I/O port into AL/AX | IN AL, 60h |
OUT | 10–14 | Write AL/AX to I/O port | OUT 60h, AL |
LEA | 2+EA | Load effective address (no bus cycle) | LEA BX, [SI+10] |
LDS | 16+EA | Load DS:reg from far pointer in memory | LDS SI, [2000h] |
LES | 16+EA | Load ES:reg from far pointer in memory | LES DI, [2000h] |
XLATB | 11 | AL = DS:[BX+AL] — table lookup via BX+AL | XLATB |
LAHF | 4 | Load SF/ZF/AF/PF/CF into AH bits 7/6/4/2/0 | LAHF |
SAHF | 4 | Store AH into SF/ZF/AF/PF/CF (used after 8087 FSTSW) | SAHF |
CBW | 2 | Sign-extend AL into AX | CBW |
CWD | 5 | Sign-extend AX into DX:AX (for IDIV) | CWD |
2. Arithmetic Instructions
In-depth coverage: Flag Register · Instruction Timing
| Instruction | Clocks | Explanation | Example |
|---|---|---|---|
ADD | 3–9+EA | Add; sets CF OF SF ZF PF AF | ADD AX, BX |
ADC | 3–9+EA | Add with carry (for 32-bit multi-word addition) | ADC AX, BX |
SUB | 3–9+EA | Subtract; sets CF OF SF ZF PF AF | SUB AX, BX |
SBB | 3–9+EA | Subtract with borrow (multi-word subtraction) | SBB AX, BX |
INC | 2–3 | Increment by 1; does NOT change CF | INC AX (2), INC AL (3) |
DEC | 2–3 | Decrement by 1; does NOT change CF | DEC BX |
NEG | 3–16+EA | Two’s complement negation | NEG AX |
CMP | 3–9+EA | Subtract and set flags; result discarded | CMP AX, BX |
MUL | 70–133 | Unsigned multiply; result in AX (8-bit) or DX:AX (16-bit) | MUL BL (70–77) / MUL BX (118–133) |
IMUL | 80–154 | Signed multiply; same result placement as MUL | IMUL BL (80–98) |
DIV | 80–162 | Unsigned divide AX (8-bit) or DX:AX (16-bit); AL=quotient AH=rem | DIV BL |
IDIV | 101–184 | Signed divide; use CWD to set up DX:AX before dividing | IDIV BL |
DAA | 4 | Decimal adjust AL after packed BCD addition | ADD AL,BL / DAA |
DAS | 4 | Decimal adjust AL after packed BCD subtraction | SUB AL,BL / DAS |
AAA | 8 | ASCII adjust AL after unpacked BCD addition | ADD AL,'3' / AAA |
AAS | 8 | ASCII adjust AL after unpacked BCD subtraction | SUB AL,BL / AAS |
AAD | 60 | Convert AH:AL unpacked BCD to binary before DIV | AAD / DIV BL |
AAM | 83 | Convert AL binary to AH:AL unpacked BCD after MUL | MUL BL / AAM |
3. Logical Instructions
In-depth coverage: Flag Register (CF and OF always cleared by logic ops)
| Instruction | Clocks | Explanation | Example |
|---|---|---|---|
AND | 3–9+EA | Bitwise AND; clears CF and OF | AND AX, BX |
OR | 3–9+EA | Bitwise OR; clears CF and OF | OR AX, BX |
XOR | 3–9+EA | Bitwise XOR; XOR reg,reg zeroes a register in 3 clocks | XOR AX, AX |
NOT | 3–16+EA | Bitwise complement; does NOT affect any flags | NOT AX |
TEST | 3–9+EA | AND without storing result; sets ZF if no bits match mask | TEST AX, 0001h |
4. Shift and Rotate Instructions
In-depth coverage: Register Reference (CL is mandatory for variable count)
| Instruction | Clocks | Explanation | Example |
|---|---|---|---|
SHL/SAL | 2 / 8+4×CL | Shift left; multiply by 2 per bit; MSB goes to CF | SHL AX, 1 / SHL AX, CL |
SHR | 2 / 8+4×CL | Logical shift right; zero fills MSB; LSB to CF | SHR AX, 1 |
SAR | 2 / 8+4×CL | Arithmetic shift right; sign bit replicated; signed divide by 2 | SAR AX, 1 |
ROL | 2 / 8+4×CL | Rotate left; MSB wraps to LSB and to CF | ROL AL, 1 |
ROR | 2 / 8+4×CL | Rotate right; LSB wraps to MSB and to CF | ROR AL, 1 |
RCL | 2 / 8+4×CL | Rotate left through carry; CF participates in rotation | RCL AL, 1 |
RCR | 2 / 8+4×CL | Rotate right through carry | RCR AL, 1 |
5. Branch / Jump Instructions
In-depth coverage: Flag Register (flag conditions for each jump)
| Instruction | Clocks | Explanation | Example |
|---|---|---|---|
JMP | 15 | Unconditional jump (near/short); flushes prefetch queue | JMP label |
JE/JZ | 16/4 | Jump if equal/zero (ZF=1); 16 taken, 4 not taken | JE LABEL |
JNE/JNZ | 16/4 | Jump if not equal/zero (ZF=0) | JNE LABEL |
JC/JB/JNAE | 16/4 | Jump if carry/below (CF=1) — unsigned less than | JC LABEL |
JNC/JNB/JAE | 16/4 | Jump if no carry (CF=0) | JNC LABEL |
JA/JNBE | 16/4 | Jump if above (CF=0 AND ZF=0) — unsigned greater than | JA LABEL |
JL/JNGE | 16/4 | Jump if less (SF≠OF) — signed less than | JL LABEL |
JGE/JNL | 16/4 | Jump if greater or equal (SF=OF) | JGE LABEL |
JG/JNLE | 16/4 | Jump if greater (ZF=0 AND SF=OF) — signed | JG LABEL |
JLE/JNG | 16/4 | Jump if less or equal (ZF=1 OR SF≠OF) | JLE LABEL |
JO/JNO | 16/4 | Jump if overflow / no overflow (OF=1/0) | JO LABEL |
JS/JNS | 16/4 | Jump if sign / no sign (SF=1/0) | JS LABEL |
JP/JPE | 16/4 | Jump if parity even (PF=1) | JP LABEL |
JNP/JPO | 16/4 | Jump if parity odd (PF=0) | JNP LABEL |
JCXZ | 18/6 | Jump if CX=0 (does not affect flags); use before LOOP | JCXZ done |
LOOP | 17/5 | Decrement CX, jump if CX≠0; DEC CX+JNZ is faster (15) | LOOP START |
LOOPE/LOOPZ | 18/6 | Loop while CX≠0 AND ZF=1 | LOOPE LABEL |
LOOPNE/LOOPNZ | 19/5 | Loop while CX≠0 AND ZF=0 | LOOPNE LABEL |
6. String Instructions
In-depth coverage: Addressing Modes & String Instructions
| Instruction | Clocks | Explanation | Example |
|---|---|---|---|
MOVSB/W | 18/17×CX | Move byte/word DS:SI→ES:DI, adjust SI+DI per DF | REP MOVSB |
CMPSB/W | 22/22×CX | Compare DS:SI with ES:DI; set flags; adjust SI+DI | REPE CMPSB |
SCASB/W | 15/15×CX | Compare AL/AX with ES:DI; set flags; adjust DI | REPNE SCASB |
LODSB/W | 12 | Load DS:SI into AL/AX, adjust SI | LODSB |
STOSB/W | 11/11×CX | Store AL/AX to ES:DI, adjust DI; REP STOSW fastest fill | REP STOSB |
REP | — | Repeat while CX≠0; decrement CX each iteration | REP MOVSB |
REPE/REPZ | — | Repeat while CX≠0 AND ZF=1 | REPE CMPSB |
REPNE/REPNZ | — | Repeat while CX≠0 AND ZF=0 | REPNE SCASB |
7. Flag Manipulation Instructions
In-depth coverage: Flag Register
| Instruction | Clocks | Explanation | Example |
|---|---|---|---|
CLC | 2 | Clear carry flag (CF=0) | CLC |
STC | 2 | Set carry flag (CF=1) | STC |
CMC | 2 | Complement carry flag (CF = NOT CF) | CMC |
CLD | 2 | Clear direction flag; string ops auto-increment SI/DI | CLD |
STD | 2 | Set direction flag; string ops auto-decrement SI/DI | STD |
CLI | 2 | Clear interrupt enable flag; blocks maskable INTR interrupts | CLI |
STI | 2 | Set interrupt enable flag; allows hardware interrupts | STI |
LAHF | 4 | Load SF/ZF/AF/PF/CF into AH | LAHF |
SAHF | 4 | Store AH into SF/ZF/AF/PF/CF | SAHF |
8. Control Transfer Instructions
In-depth coverage: Stack Operations · Interrupt System
| Instruction | Clocks | Explanation | Example |
|---|---|---|---|
CALL | 19/28 | Push return address, jump to target (near 19, far 28) | CALL 3000h |
RET | 20 | Near return: pop IP from stack | RET / RET 4 |
RETF | 32 | Far return: pop IP then CS from stack | RETF |
INT n | 51 | Push FLAGS+CS+IP, jump via IVT[n×4] | INT 21h |
INTO | 53/4 | Interrupt if OF=1 (triggers INT 4); 4 clocks if OF=0 | INTO |
IRET | 44 | Pop IP, CS, FLAGS from stack; only correct ISR exit | IRET |
9. Miscellaneous Instructions
| Instruction | Clocks | Explanation | Example |
|---|---|---|---|
NOP | 3 | No operation (XCHG AX,AX); used for timing pads | NOP |
HLT | 2 | Halt CPU until interrupt or reset | HLT |
WAIT/FWAIT | 3+ | Stall until 8087 BUSY pin deasserts; required after FSTP | FWAIT |
ESC | 8+EA | Escape opcode (D8h–DFh): 8086 passes to 8087 coprocessor | ESC 0, [BX] |
LOCK | +0 | Prefix: assert LOCK signal during next instruction (bus lock) | LOCK INC [BX] |
CBW | 2 | Sign-extend AL into AX | CBW |
CWD | 5 | Sign-extend AX into DX:AX (prepare for IDIV) | CWD |
10. 8087 Coprocessor Instructions
Full treatment including register stack, data formats, and worked examples: Data Directives & 8087 FPU · Hardware interface (ESC/BUSY/WAIT): BIU/EU Architecture
| Instruction | Explanation | Example |
|---|---|---|
FLD src | Push mem32/64/80 or ST(i) onto FPU stack; ST(0) = src | FLD my_dq_var |
FST / FSTP | Store ST(0) to memory; FSTP also pops stack | FSTP result |
FXCH ST(i) | Exchange ST(0) with ST(i); makes any register top-of-stack | FXCH ST(2) |
FILD / FIST | Load/store integer (16/32/64-bit) converting to/from float | FILD my_word |
FLD1 / FLDZ / FLDPI | Push constant 1.0 / 0.0 / π onto stack | FLDPI |
FADD / FSUB / FMUL / FDIV | Floating-point arithmetic; operates on ST(0) with src | FADD ST(1) |
FABS / FCHS / FSQRT | Absolute value / negate / square root of ST(0) | FSQRT |
FCOM / FTST | Compare ST(0) with src or 0.0; sets C0/C2/C3 in Status Word | FTST / FSTSW / SAHF |
FINIT / FWAIT | Initialize 8087 / stall 8086 until 8087 BUSY=LOW | FINIT |
FPTAN / FPATAN / FYL2X | Transcendentals: tan, arctan, Y×log₂(X) | FPTAN |
11. 80286+ Protected Mode Instructions
Full treatment of protected mode segmentation, GDT/LDT, and privilege rings: Memory Segmentation
| Instruction | Available | Explanation | Example |
|---|---|---|---|
ENTER n, 0 | 80186+ | Automates PUSH BP / MOV BP,SP / SUB SP,n stack frame setup | ENTER 4, 0 |
LEAVE | 80186+ | Automates MOV SP,BP / POP BP (epilogue); slower than explicit pair | LEAVE |
BOUND | 80186+ | Check array index in reg against bounds in memory; INT 5 if out of range | BOUND AX, [limits] |
LGDT / LIDT | 80286+ | Load 6-byte descriptor (base+limit) into GDTR / IDTR register | LGDT [gdt_desc] |
LLDT | 80286+ | Load selector into LDTR (ring 0 only) | LLDT AX |
LMSW / SMSW | 80286+ | Load/store Machine Status Word; LMSW with PE=1 enters protected mode | LMSW AX |
ARPL | 80286+ | Adjust RPL field of selector so it ≥ caller’s privilege level | ARPL AX, BX |
VERR / VERW | 80286+ | Verify selector is readable/writable at current privilege; sets ZF | VERR AX |
LAR | 80286+ | Load access rights byte of a descriptor into register | LAR AX, BX |
LSL | 80286+ | Load segment limit from descriptor into register | LSL AX, BX |